Electrically erasable programmable read only memory (EEPROM) structures are commonly used in integrated circuits for non-volatile data storage. An EEPROM device structure commonly includes a floating gate for storing charge. Charge can be forced into the floating gate structure or removed from the floating gate structure using control voltages. The conductivity of the channel underlying the floating gate is altered by the presence of charges stored in the floating gate. The conductivity difference is represented by a shift in the threshold voltage (VT) associated with the device in the two different states. The difference in conductivity due to a charged or uncharged floating gate can be sensed, thus allowing binary memory states to be determined.
In many prior art non-volatile memory devices, the floating gate is formed from a uniform layer of material such as polysilicon. In such prior art device structures, a thin tunnel dielectric layer beneath the floating gate presents the problem of charge leakage from the floating gate to the underlying channel through defects in the thin tunnel dielectric layer. Such charge leakage can lead to degradation of the memory state stored within the device and is therefore undesirable. In order to avoid such charge leakage, the thickness of tunnel dielectric is often increased. However, a thicker tunnel dielectric requires higher programming and erasing voltages for storing and removing charge from the floating gate as the charge carriers must pass through the thicker tunnel dielectric. In many cases, higher programming voltages increase power consumption and may require the implementation of charge pumps in order to increase the supply voltage to meet programming voltage requirements. Such charge pumps consume a significant amount of die area for the integrated circuit and therefore reduce the memory array area efficiency and increase overall costs.
Because of the above described problems, other materials are being developed to substitute for the typical floating gate charge storage regions. In order to reduce the required thickness of the tunnel dielectric and improve the area efficiency of the memory structures by reducing the need for charge pumps, the uniform layer of material used for the floating gate may be replaced with a plurality of nanoclusters, which operate as isolated charge storage elements. Such nanoclusters are also often referred to as nanocrystals, as they may be formed of silicon crystals. In combination, the plurality of nanoclusters provide adequate charge storage capacity while remaining physically isolated from each other such that any leakage occurring with respect to a single nanocluster via a local underlying defect does not cause charge to be drained from other nanoclusters (by controlling average spacing between nanoclusters, it can be ensured that there is no lateral charge flow between nanoclusters in the floating gate). However, a charge storage layer formed from nanoclusters or nanocrystals will not store as much charge as a floating gate formed from polysilicon. Because the nanocrystals will not store as much charge, the voltage difference between programmed and erased states may be relatively small, leading to sensing and reliability problems.
Therefore, it is desirable to provide an integrated circuit device that will store more charge than a nanocrystal memory device and yet provide low voltage program and erase operations.